Teaching Assistant: Scot Kronenfeld
Office: B630 Engineering Hall
Office hours: Mon. and Wed. 12-12:55 PM
Office phone: 263-1572
E-mail: swkronenfeld@wisc.edu
John L. Hennessy and David A. Patterson, Computer Organization and Design: The Hardware/Software Interface, 2nd Edition, Morgan Kaufmann Publishers, 1998.
There will be five homework assignments, approximately one assignment two weeks apart. Some of the assignments will require the use of the Mentor Graphics design automation tools. There will also be a course project that will involve the design of a small CPU. Students will have accounts to run the Mentor tools in CAE.Some assignments and the project should be done in groups of three students. (When an assignment is handed out, we will indicate whether you should do it alone, or in a group.) Each member of a group is expected to participate in the solution of the entire assignment. All assignments will not be weighted equally. The approximate weight of each assignment will be specified when the assignment is handed out.
All logic diagrams should be drawn using either the Mentor Graphics Tool Suite or other tools capable of producing high quality logic diagrams.
Assignments are due by 5:00 P.M on the due date. No late assignments will be accepted.
The discussion session is scheduled from 5:00-6:00 PM on Wednesdays in Room 1263 Comp. Sci. Discussions will be used for question answering, exam review, and covering any topics as requested by members of the class. On weeks when the discussion session does not meet, the TA will have an additional office hour at the same time.
There will be two exams, of equal weight. Exam I will be in class on Tuesday, Mar. 9, 2004.
Exam II will be during the scheduled final exam slot on Wed., May 12, 2004, at 12:25 PM
Homework 15%
Exam I 30%
Project 25%
Exam II 30%
Date(s) Topic(s) Text Sections
Jan. 20, 22 Introduction; Architecture; Performance Chapters 1 and 2
Jan. 27, 29 Instruction Sets 3.1-3.12
Feb.3, 5 Arithmetic I 4.1-4.5
Feb. 10 Datapath Design 5.1-5.3
Feb. 12, 17, 19
Control 5.4-5.9; Appendix C
Feb. 24, 26 Pipelining 6.1-6.7
Mar. 2 Superscalar processors 6.8-6.9
Mar. 4 Review
Mar. 9 Midterm
Mar. 25, 30 Cache Memories 7.1-7.3, 7.5
Apr. 1 Main Memory 7.1; B31-B35; handout
Apr. 6, 8 Virtual Memory 7.5,7.6
Apr. 8,13 Arithmetic II 4.6-4.10
Apr. 20,22 Input/Output 8.1-8.7
Apr. 29 Multiprocessors 9.1-9.9
May 4, 6 Catch-up, Review