Projects that furhter the
student's research are encouraged.
Virtual Machine Architectures, Implementations,
Table of Contents
James E. Smith
Architectures, Implementations, and Applications (draft version), J. E.
Smith and Ravi Nair, to be published by Morgan Kaufmann, 2005.
- Reference Course Material
1) John L. Hennessy and David A. Patterson, Computer
Architecture: A Quantitative
Approach, 2nd Edition, Morgan Kaufmann
2) Andrew S. Tanenbaum, Modern Operating Systems, 2nd Edition, Prentice
The default project is to write a paper that surveys an area within
Web site created April 21, 2005
Class will meet on the following schedule.
April 26, May 3 9am -- 12 noon
May 9, 11, 18 3pm -- 5pm
May 24, 31 9am -- 12
1. Introduction (1 hour)
Architecture, abstraction, virtualization
VM types and applications
2. Emulation: Interpretation and Binary
Translation (3 hours)
Design issues and alternatives
Case Study: Shade
3. Process VMs (3 hours)
Handling OS calls
Case studies: FX!32, WABI
4. Dynamic Optmization (3 hours)
Case studies: IA-32 EL, HP Dynamo
5. Co-Designed VMs (4 hours)
Support for speculation
Case studies: Daisy, Crusoe, rePLay, AS/400
6. System VMs (3 hours)
OS management and protection of resources
Virtualizing memory, processor, I/O
Instruction set virtualizability
Case studies: IBM VM/370, Intel x86 VMware, Vanderpool
- B. Cmelik and D. Keppel, "Shade:
A Fast Instruction-Set Simulator for Execution Profiling,"
University of Washington Technical Report, UWCSE 93-06-06.
- Baraz, L, T. Devor, O. Etzion, S. Goldenberg, A. Skaletsky, Y.
Wang, and Y. Zemach. 2003. IA-32
Execution Layer: A Two-phase Dynamic Translator Designed to Support
IA-32 Applications on Itanium based Systems, Proc.
36th Annual IEEE/ACM
International Symposium on Microarchitecture, (December), pp.
- R. J. Hookway, M. A. Herdeg, "Digital
FX!32: Combining Emulation and Binary Translation," Digital
Technical Journal, Jan. 1997, pp. 3-12.
- Hohensee, P., M. Myszewski, and D. Reese. 1996. Wabi CPU Emulation, Proceedings
of the 8th HotChips Symposium, (August) , pp. 47-65.
- B. C. Le, "An
Out-of-Order Execution Technique for Runtime Binary Translators,"
Proc. 8th ASPLOS,
1998, pp. 151-158.
- V. Bala, E. Duesterwald, S. Banerjia, "Transparent
Dynamic Optimization: The Design and Implementation of Dynamo," HP
Laboratories Technical Report HPL-1999-78, June 1999.
- K. Ebcioglu, et al., "Dynamic
Binary Translation and Optimization," IEEE Transactions on
Computers, June 2001, pp. 529-548.
- A. Klaiber, "The
Technology Behind Crusoe Processors," Transmeta Technical Brief,
- Fahs, B., S. Bose, M. Crum, B. Slechta, F. Spadini, T. Tung, S.
J. Patel, and S. S. Lumetta. 2001. Performance
Characterization of a Hardware Mechanism for Dynamic Optimization, Proc. 34th Int. Symp. Microarchitecture, (December),
- Bertsis, V. 1980. Security and
Protection of Data in the IBM System/38, Proc. 7th Annual
Symposium on Computer Architecture, (June), pp. 245-252.
- Dehnert, J. C., B. K. Grant, J. P. Banning, R. Johnson, T.
Kistler, A. Klaiber, J. Mattson. 2003. The
Transmeta Code Morphing Software: Using Speculation, Recovery, and
Adaptive Retranslation to Address Real-Life Challenges, Proc.
Int. Symp. Code Generation and Optimization, (March), pp. 15-24.
- R. Goldberg, "Formal
Requirements for Virtualizable Third Generation Architectures,"
CACM, July 1974, pp. 412-421.
- Anon. "VMware
Virtual Platform Technology White Paper", VMware Corporation, 1999.
- M. Rosenblum, "VMware's
Virtual Platform Technology," Stanford Computer Systems
Seminar, Jan. 12, 2000.
- J. Sugerman, et al., "Virtualizing
I/O Devices on VMware Workstation's Hosted Virtual Machine Monitor,"
- Intel, 2005. Intel Vanderpool Technology for IA-32 Processors (VT-x)
Preliminary Specification, Order Number C97063-001, Santa Clara, CA