Table of Contents

• Instructor Information
• Course Information
• News
• Course Outline
• Readings
• Homeworks
• Project
• Miscellaneous Links

Instructor Information

        Office: 4621 Engineering Hall
        Office hours:  2:30-3:30 PM  TR
        Office phone:  265-5737
        Email:   jes@ece.wisc.edu

        TA:  Emily Blem
        Office Hours:  1:00-2:00 PM MW
        Office:   B632 Engineering Hall
        Phone:  265-4885
        Email:  blem@wisc.edu

Course Information

• Required Course Material

• Reference Course Material

• Project

There will be a course project -- details will be provided prior to the first exam


• Examinations

The first exam will be in class on October 27
The second exam will be during the scheduled final exam period on Tuesday, Dec. 20

• Grading

Homework         15%
Exam  I              30%
Project               25%
Exam  II             30%

News

Course Outline

1. Introduction (.5 lecture)

2. Instruction Set Architecture (1.5 lectures)
    Date: Sept. 6, 8
    Reading: Text Section 1.2, Thornton , Wulf, Amdahl et al.

3. Pipelines (2 lectures)
    Date:  Sept. 13, 15
    Reading:   Text Sections 1.3, 1.4,  Chapter 2
    Reference: pipeline clocking paper, Russell (Cray-1)
    Cray-1 example powerpoint slides

3a.Pipelines: Precise Exceptions (.5 lecture)
    Date: Sept. 20
     Reading:  Smith-Pleszkun precise interrupts

4.Cache Memories (.5 lecture)
    Date: Sept. 20
    Reading:  Text Sections 3.3-3.4.3

5. Dynamic Instruction Scheduling (1 lecture)
    Date: Sept. 22
     Reading: Text Section 4.1-4.2, 5.2.4, Tomasulo
     Reference: Thornton

6. Superscalar Processor Organization (2 lectures)
      Dates: Sept. 27, Oct. 4
      Reading:  Text Sections 4.3, 5.1, 5.2, Chapter 7, Christie, Yeager 

7. Performance;   Balanced Design  (1 per page version) (1 lecture+)
    Date: Oct. 6, 11, 13
    Reading:: Text Section 1.3,   Amdahl,  Karkhanis
    Reference: John,   Kumar,  Michaud,  Wunderlich

 8. Enhancing Performance (3 lectures + or -)
    Dates: Oct.18,  20; Nov. 1, 3
    Reading:   Instruction Delivery: Text Section  9.5.3
                    Memory Disambiguation: Text Section 5.3, Chrysos and Emer
                    Branch  Prediction:  Text Sections  5.1, 9.1-9.5.2
                    Advanced Caches: Jouppi
                    Data Cache Prefetching:  Temam, Nesbit

Review Oct. 25

9. New Paradigms (2 lectures)
    Dates: Nov. 8, 10
    Reading:  Klaiber,  Cristal et al.,  Hu et al.
    Reference: Crawford/Huck IA64

10. Virtual Memory (1 lecture)
    Dates: Nov. 15
    Reading:  Text Sections  3.5, 3.6

11. Main Memory  (1 lecture)
    Dates: Nov. 17
    Reading:  Text Section 3.4.4;   Rixner et al.
    Reference: Natarajan et al.  Vogt

12. DSP and Media Processing (1 lecture)
    Dates: Nov. 22
    Reading:  Diefendorff,  Peleg
    Reference: MMX/SSE/SSE2 tutorials  DSP Tutorial;   Francis

13. Power Efficiency (2 lectures)
    Dates: Nov. 29, Dec. 1
    Reading: Mudge, Montanaro et al., Gochman et al., Karkhanis et al.
    Reference: Irwin,  Asanovic

14. I/O and Storage Systems (1 lecture)
    Dates: Dec.  8
    Reading:  Text Section 3.7;   PCI Bus Technical Summary;  PCI-X Technology Whitepaper
    Reference: SATA Technology Overview

15. Multiprocessors and Multithreading (2 lectures)

Exam II, Dec 20, 2:45PM

Readings

• International Technology Roadmap for Semiconductors (ITRS)
• J. E. Thornton, Considerations in Computer Design -- Leading up to the Control Data 6600, Control Data Corporation, 1963.
• William A. Wulf. Compilers and Computer Architecture, IEEE Computer, July 1981
• G. M. Amdahl, G. A. Blaauw, and F. P. Brooks, Jr. Architecture of the IBM System/360, IBM Journal of Research and Development, Apr. 1964. Available from IBM Research
• J. E. Smith, An Analysis of Pipeline Clocking, unpublished note.
• Russell, R. M., The CRAY-1 Computer System, Communications of the ACM, 21, 1, January 1978, pp. 63-72
• J. E. Smith and A. R. Pleszkun, Implementing Precise Interrupts in Pipelined Processors, IEEE Trans. Computers, May 1988, pp. 562-573.
• R. M. Tomasulo, An Efficient Algorithm for Exploiting Multiple Arithmetic Units, IBM Journal, January 1967, pp. 25-33.
• D. Christie, Developing the AMD-K5 architecture, IEEE Micro, April 1996, pp. 16-27.  Available online via UW Library site
  
• K. C. Yeager, The Mips R10000 superscalar microprocessor, IEEE Micro, April 1996, pp. 28-41.  Available online via UW library site
• T. Karkhanis and J. E. Smith, A First-Order Superscalar Processor Model,  31st Int. Symposium on Computer Architecture, pp. 338-349, June 2004
• L. K. John,  More on finding a single number to indicate overall performance of a benchmark suite, ACM SIGARCH Computer Architecture News, 2004.
• D. J. Kuck , B. Kumar,  A system model for computer performance evaluation, Proceedings of the 1976 ACM SIGMETRICS conference on Computer performance modeling measurement and evaluation, p.187-199, March 29-31, 1976.
• RE Wunderlich, TF Wenisch, B Falsafi, J. C.  Hoe,  SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling, 2003 Int. Symp. on Computer Architecture
• P Michaud, A Seznec, S Jourdan, Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors, 1999 Parallel Architecture and Compiliation Technology (PACT). pp. 2-10.
• G. M. Amdahl, Validity of the single processor approach to achieving large scale computing capabilities, AFIPS Conference Proceedings, 1967
• G. Z. Chrysos, J. S. Emer, Memory dependence prediction using store sets, Int. Symposium on Computer Architecture, 1998
N. Jouppi, Improving Direct Mapped Cache Performance by the Addition of  a Small Fully Associative Cache and Prefetch Buffers, 17th Annual International
Symposium on Computer Architecture, pages 364–373,  May 1990..
• D. G.  Perez, G. Mouchard, O. Temam, MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms,  37th International Symposium on Microarchitecture,  pp. 43-54
• K. J. Nesbit, J. E. Smith, Data Cache Prefetching Using a Global History Buffer,  IEEE Micro, Jan./Feb. 2005.
• A. Klaiber, The Technology Behind Crusoe Processors, Transmeta Technical Brief, 2000.
• J. Crawford, J. Huck, Next Generation Instruction Set Architecture
  
• Shiliang Hu, et al.,  An Approach for Implementing Efficient Superscalar CISC Processors, to appear 2006 Int. Symp. on High Performance Computer Architecture.
  
• A. Cristal, et al., Kilo-Instruction Processors: Overcoming the Memory Wall, IEEE Micro, pp. 48-57, May/Jume 2005.
• S. Rixner et al., “Memory Access Scheduling,” Proc. 27th Ann. Int’l Symp. Computer Architecture, IEEE CS Press, 2000, pp. 128-138.
• Chitra Natarajan, et al.,  A study of performance impact of memory controller features in multi-processor server environment. WMPI 2004: 80-87
• Peter Vogt, "Fully Buffered DIMM  Server Memory Architecture", Intel Developers Forum, Feb. 2004.
• H. Francis, "ARM DSP-Enhanced Functions", ARM Whitepaper, May 2001.
• K. Diefendorff, et al., "Altivec Extension to PowerPC Accerates Media Processing,"  IEEE Micro, Mar.-Apr. 2000.
• A. Peleg, et al., "Intel MMX for Multimedia PCs,"  CACM, Jan. 1997.
• DSP tutorial
• Quexal MMX/SSE/SSE2 tutorials
• T. Mudge, "Power: A First Class Design Constraint for Future Architectures", High Performance Computer Conference, Dec. 2000.
  
• Montanaro, et al. ,"A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor", Digital Technical Journal,  vol. 9, no. 1, 1997, pp. 49-62.
• Gochman et al., "The Intel Pentium M Processor: Microarchitecture and Performance," Intel Technical Journal, May 2003, pp. 21-36.
• T. Karkhanis, J. E. Smith, P.  Bose, "Saving Energy with Just In Time Instruction Delivery", Int. Symp. on Low Power Electronics and Design, 2002, pp. 178-183.
• K. Asanovic, Embedded Computing, ppt slides from MIT course lecture.
• M. J. Irwin and V Narayanan Low Power Tutorial, ISCA 2000
• SATA Technology Overview
  
• PCI Bus Technical Summary
• Dell PCI-X Technology Whitepaper
• IBM Power4 System Microarchitecture Whitepaper
• A. Charlesworth -- The Sun Fireplane System Interconnect,  SC2001.
  

Project

• Dates

• Assignment

• Link to wattch and sim-alpha (courtesy of Tejas Karkhanis)
  

Homework

Miscellaneous Links

• Computer Architecture Colloquia
• SimpleScalar Architectural Research Tool Set v2.0
• SimpleScalar Architectural Research Tool Set v3.0
• SimpleScalar.org
• SimpleScalar Tutorial from Micro 30
• SimpleScalar Hacker's Tutorial
• Standard Performance Evaluation Corporation (SPEC)
• Streams Benchmark memory bandwidth kernels
• x86 instruction descriptions, in a reasonably easy-to-use online form (under "Instruction Set")
• IBM Daisy Project; information regarding the IBM Daisy VLIW system
• Streams benchmark site