1. Introduction (1 lecture)
VM types and applications
Summary of key design issues
Course Roadmap
2. Computer Architecture (1 lecture)
Computer Architecture(s)
Principal interfaces: ISA, ABI
Managing and protecting hardware resources
3. Emulation: interpretation and binary translation (2
lectures)
Fetch-execute interpretation
Binary Translation
Translation caching
Case Studies: Shade, UQDBT
4. ABI VMs (3 lectures)
VM Integration
Phased translation
Precise traps
Self-referencing and modifying code
Case studies: HP Shogun, FX!32, WABI
5. Dynamic Optmization (1 lecture)
Relationship to translation
Case study: HP Dynamo
6. Hardware Assisted Profiling (1 lecture)
Profile buffers
Path profiling
Stratified sampling
Case Study: ProfileMe
7. OS VMs (3 lectures)
OS management and protection of resources
Virtualizing memory, processor, I/O
Instruction set virtualizability
Case studies: IBM VM/370 and Intel x86 VMware
8. Whole System VMs (1 lecture)
ISA VMs
Hosted VMs (user mode VMMs)
Virtual memory issues
Native mode execution
System mode VMs
Case Studies: SimOS, Daisy Simulator
9. Co-Designed VMs (3 lectures)
Microarchitecture
Support for speculation
Precise interrupts
Case studies: Daisy, Crusoe
10. Hardware Adaptivity (2 lectures)
Configurable Hardware
Hardware performance monitoring and control
Configuration algorithms
Readings
J. E. Smith, "An
Overview of Virtual Machine Architectures"
-
Emulation: Interpretation and Binary Translation
B. Cmelik and D. Keppel, "Shade:
A Fast Instruction-Set Simulator for Execution Profiling," University
of Washington Technical Report, UWCSE 93-06-06.
D. Ung and Cristina Cifuentes, "Optimising
Hot Paths in a Dynamic Binary Translator," Second Workshop on Binary
Translation, Philadelphia, Pennsylvania, October 19, 2000, ACM.
B. C. Le, "An
Out-of-Order Execution Technique for Runtime Binary Translators,"
Proc. 8th ASPLOS, 1998, pp. 151-158.
-
ABI VMs
R. J. Hookway, M. A. Herdeg, "Digital
FX!32: Combining Emulation and Binary Translation," Digital Technical
Journal, Jan. 1997, pp. 3-12.
P. Hohensee, et al., "Wabi
Cpu Emulation", Hot Chips VIII.
-
Dynamic Optimization
V. Bala, E. Duesterwald, S. Banerjia, "Dynamo:
A Transparent Dynamic Optimization System," Proc. of the ACM SIGPLAN
'00 Conference on Programming Language Design and Implementation, 2000,
pp. 1-12.
-
Hardware Assisted Profiling
Thomas M. Conte et al., "Accurate
and practical profile-driven compilation using the profile buffer",
Proceedings of the 29th Annual International Symposium on Microarchitecture,
December 1996, pp. 36-45
S. Sastry, R. Bodik, J. E. Smith, "Rapid
Profiling via Stratified Sampling," 28th Int. Symposium on Computer Architecture,"
June 2001, pp. 278-289.
J. Dean, et al, "ProfileMe:
Hardware Support for Instruction-Level Profiling on Out-of-Order Processors,"
30th Int. Symp. on Microarchitecture, Dec. 1997, pp. 292-302.
-
OS VMs
R. Goldberg, "A
Survey of Virtual Machine Research," IEEE Computer, June 1974, pp.
34-45.
R. Goldberg, "Formal
Requirements for Virtualizable Third Generation Architectures," CACM,
July 1974, pp. 412-421.
K. Lawton, "Running
Multiple Operating Systems Concurrently on an IA32 PC Using Virtualization
Techniques"
Anon. "VMware
Virtual Platform Technology White Paper", VMware Corporation, 1999.
M. Rosenblum, "VMware's
Virtual Platform Technology," Stanford Computer Systems Seminar,
Jan. 12, 2000.
J. Sugerman, et al., "Virtualizing
I/O Devices on VMware Workstation's Hosted Virtual Machine Monitor,"
USENIX 2001.
-
Whole System VMs
M. Rosenblum, et al, "Complete
Computer System Simulation: the SimOS Approach", IEEE Parallel and
Distributed Technology, Fall 1995.
E. R. Altman and K. Ebcioglu, "Simulation
and Debugging of Full System Binary Translation".
-
Co-Designed VMs
K. Ebcioglu, et al., "Dynamic
Binary Translation and Optimization," IEEE Transactions on Computers,
June 2001, pp. 529-548.
A. Klaiber, "The
Technology Behind Crusoe Processors," Transmeta Technical Brief, 2000.
-
Hardware Adaptivity
R. Balasubramonian, D.H. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas,
"Memory
Hierarchy Reconfiguration for Energy and Performance in General-Purpose
Processor Architectures," 33rd International Symposium on Microarchitecture,
pp. 245-257, December 2000.
T. Juan, et al., "Dynamic
History-Length Fitting: A third level of adaptivity for branch prediction,"
25th Annual Int. Symp. on Computer Architecture, 1998, pp. 155-166.
Michael Huang, et al. "A
Framework for Dynamic Energy Efficiency and Temperature Management,"
33rd International Symposium on Microarchitecture (MICRO), December 2000.
A. Dhodapkar and J. E. Smith, "Managing
Multi-Configuration Hardware via Dynamic Working Set Analysis," 29th
Int. Symp. on Computer Architecture, 2002.