Multicore Architectures

CANS Master Course

April 7-11, 2008

Table of Contents

News

Web page created Mar. 29, 2008

             

Instructor Information

Prof. James E. Smith
Email:     jes@ece.wisc.edu   put "UPC" somewhere in subject line.
     

Calendar

Monday Apr. 7           10-12:00          Rm A6205

Tuesday Apr. 8           10-12:00          Rm A6203

Wednesday Apr. 9      11-13:00          Rm A6203

Thursday Apr. 10        10-12:00          Rm A6203

Friday  Apr. 11           15-17:00          Rm A6205

 

Course Outline

1. Introduction (1 hour)

Date: April  7

Reading: Olukotun et al.

 

2. Multicore Memory Hierarchy (2 hours)

Dates:  April 7,8

Reading:  J. E. Smith notes; Dubois et al., Barroso et al.

3. Interconnects (1 hour)

Date:  April 8

Reading:  Kumar et al. (ISCA)

 

4. Shared Resources (3 hours)

Dates:  April 9,10

Reading:  Suh et al., Beckman et al., Nesbit et al.

 

5. Heterogeneous Cores  and catch-up (1 hour)

Date:  April 10

Reading: Kumar et al. (Computer)

 

6. Case Studies (2 hours)

          Date: April 11

          Reading: TBD

 

Papers

        Introduction

1.      K. Olukotun, et al., “The Case for a Single-Chip Multiprocessor,” ASPLOS-7, October 1996. 

       Multicore Memory Hierarchies

2.      J. E. Smith,  Chapter 4 notes

3.      M. Dubois, C. Scheurich, and F. A. Briggs, “Synchronization, Coherence, and Event Ordering in Multiprocessors”, IEEE Computer, vol. 21, pp. 9-21, February 1988.

4.      L. Barroso et al. Piranha: A Scalable Architecture Based on Single Chip Multiprocessing,  Proc. 27th International Symposium on Computer Architecture, June 2000.

       Interconnects 

1.      Kumar, R., V. Zyuban, and D. M. Tullsen, “Interconnections in Multicore Architectures: Understanding Mechanisms, Overheads and Scaling,”  32nd Int’l Symp. on Computer Architecture, June. 2005.

 

  Shared Resources

2.      Suh, G. E., L. Rudolph, and S. Devadas, “Dynamic Partitioning of Shared Cache Memory,” The Journal of Supercomputing, pp,  7–26, 2004.

3.      Beckman, B., M. Marty, and D. Wood, “ASR: Adaptive Selective Replication for CMP Caches”, MICRO-39,  Dec. 2006.*

4.      K. Nesbit, J. Laudon, and J. E. Smith, “Virtual Private Caches,” 34th Int. Symposium on Computer Architecture, June 2007.

  Heterogeneous CMPs

5.      Kumar, R., et al., “Heterogeneous Chip Multiprocessors”, IEEE Computer, pp. 32-38, Nov. 2005.

       Case Studies

6.      P. Kongetira, et al., Niagara: A 32-way Multithreaded SPARC Processor, IEEE Micro, March/April 2005, pages 21-29.

7.      H. McGhan, “Niagara 2 Opens the Floodgates,” Microprocessor Report, Nov. 2006.

8.      J. D. Davis, et al., Maximizing CMT Throughput with Mediocre Cores, In Proceeedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, Sep. 2005, pages 51-62.

9.      J. A. Kahle, et al., "Introduction to the Cell Multiprocessor",  IBM Journal of Research and Development, pp. 589-604,  July/Sept. 2005.

10.  M. Day and P. Hofstee, "Hardware and Software Architectures for the Cell Broadband Engine Processor, "  Codes+ISSS Conference, Sept. 2005.

11.  Mendelson, A., et al.,   “CMP Implementation in Systems Based on the Intel® Core™ Duo Processor”, Intel Technology Journal, pp. 99-107, May 15, 2006. 

12.  Keltcher, C.N., McGrath, K.J., Ahmed, A., and Conway, P., “The AMD Opteron processor for multiprocessor servers”,  IEEE Micro, 2003.

13.  Le, H. Q., et al., “IBM Power6 Microarchitecture,”   IBM Journal of Research and Development, pp. 639-662,  Nov. 2007.

Project

Four groups (2 persons each) will present a case study in class the last day (Apr. 10).  The case studies will be include:

            Sun Niagara

            IBM Cell

            Intel Core and AMD Opteron

            IBM Power

Miscellaneous Links